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d a t a sh eet preliminary speci?cation file under integrated circuits, ic22 1996 nov 07 integrated circuits saa7124; saa7125 digital video encoder (eco-denc)
1996 nov 07 2 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 features monolithic cmos 5 v device digital pal/ntsc encoder system pixel frequency 13.5 mhz accepts mpeg decoded data on 8-bit wide input port. input data format cb, y, cr etc. (ccir 656) four dacs for cvbs (10-bit resolution), rgb (9-bit resolution) operating at 27 mhz; rgb sync on cvbs optionally 2 times cvbs and y, c (all 10-bit resolution) available simultaneously closed captioning encoding on-chip yuv to rgb dematrix optionally to be by-passed for cr, y, cb output on rgb dacs fast i 2 c-bus control port (400 khz) encoder can be master or slave programmable horizontal and vertical input synchronization phase, via input pins or auxiliary codes at mp data port programmable horizontal sync output phase internal 100/75 colour bar generator (cbg) macrovision pay-per-view copy protection system as option, also partly used for rgb output. this applies to saa7124 only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductor sales office for more information controlled rise and fall times of output syncs and blanking down-mode of dacs lqfp64 (v1 devices only), qfp80 or plcc84 package. general description the saa7124; saa7125 encodes digital yuv video data to an ntsc or pal cvbs plus rgb or alternatively to s-video and cvbs output. optionally, the yuv to rgb dematrix can be by-passed providing the digital-to-analog converted cb, y, cr signals instead of rgb. the circuit accepts ccir compatible yuv data with 720 active pixels per line in 4:2:2 multiplexed formats, for example mpeg decoded data. it includes a sync/clock generator and on-chip digital-to-analog converters (dacs). ordering information note 1. lqfp64 package for v1 devices only. type number package (1) name description version SAA7124WP; saa7125wp plcc84 plastic leaded chip carrier; 84 leads sot189-2 saa7124hz; saa7125hz lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 saa7124h; saa7125h qfp80 plastic quad ?at package; 80 leads (lead length 2.35 mm); body 14 20 2.8 mm sot318-3
1996 nov 07 3 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 quick reference data symbol parameter min. typ. max. unit v dda analog supply voltage 4.75 5.0 5.25 v v ddd digital supply voltage 4.75 5.0 5.25 v i dda analog supply current - tbf 60 ma i ddd digital supply current - tbf 100 ma v i input signal voltage levels ttl compatible v o(p-p) analog output signal voltages y, c, cvbs and rgb without load (peak-to-peak value) - 2.0 - v r l load resistance 80 --w ile lf integral linearity error -- 4 lsb dle lf differential linearity error -- 1 lsb t amb operating ambient temperature 0 - +70 c
1996 nov 07 4 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 block diagram fu ll pagewidth mgg550 8 2 8 i 2 c-bus interface i 2 c-bus control 8 i 2 c-bus control 8 i 2 c-bus control 8 2 2 i 2 c-bus control i 2 c-bus control i 2 c-bus control 8 i 2 c-bus control data manager encoder sync clock output interface mode rgb processor internal control bus cbcr y c clock and timing d a 1 84 83 4 37 50 35 36 46 45 44 48 54, 57, 60, 64, 74 53, 75 73 67 62 59 56 65 61 58 55 63, 68 52, 76 77 78 3, 15, 24, 30, 39, 42, 51, 79, 81 5, 14, 22, 29, 38, 41, 49, 80, 82 2, 16 to 21, 23, 40, 43, 47, 66, 70, 72 y cbcr 25 to 28, 31 to 34 mp7 to mp0 reset sda scl sa rtci cdir rcv1 rcv2 v dddo (5) xtalo xtali llc v dda1 to v dda5 v refh1 v refh2 cvbs (1) v ssa1 res res res res red (2) green (3) blue (4) cur1 cur2 v refl1 v refl2 ap 69, 71 res sp n.c. v ddd1 to v ddd9 v ssd1 to v ssd9 y saa7124 saa7125 fig.1 block diagram; plcc84. (1) alternatively y or cvbs. (2) alternatively chroma or cr. (3) alternatively cvbs or yin. (4) alternatively cvbs or cb. (5) v1 devices only.
1996 nov 07 5 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fu ll pagewidth mgg551 8 2 8 i 2 c-bus interface i 2 c-bus control 8 i 2 c-bus control 8 i 2 c-bus control 8 2 2 i 2 c-bus control i 2 c-bus control i 2 c-bus control 8 i 2 c-bus control data manager encoder sync clock output interface mode rgb processor internal control bus cbcr y c clock and timing d a 57 56 55 59 21 31 19 20 28 27 26 29 34, 36, 38, 41, 46 33, 47 45 42, 43 39 37 35 40, 44 32, 48 49 50 6, 8, 14, 23, 25, 51, 53, 58 5, 7, 13, 22, 24, 30, 52, 54, 60 y cbcr 9 to 12, 15 to 18 mp7 to mp0 reset sda scl sa rtci cdir rcv1 rcv2 v dddo xtalo xtali llc v dda1 to v dda5 v refh1 v refh2 cvbs (1) v ssa2 red (2) green (3) blue (4) cur1 cur2 v refl1 v refl2 ap sp v ddd1 to v ddd9 v ssd1 to v ssd8 y saa7124 saa7125 2 fig.2 block diagram; tqfp64, v1 devices only. (1) alternatively y or cvbs. (2) alternatively chroma or cr. (3) alternatively cvbs or yin. (4) alternatively cvbs or cb.
1996 nov 07 6 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 a gewidth mgg552 8 2 8 i 2 c-bus interface i 2 c-bus control 8 i 2 c-bus control 8 i 2 c-bus control 8 2 2 i 2 c-bus control i 2 c-bus control i 2 c-bus control 8 i 2 c-bus control data manager encoder sync clock output interface mode rgb processor internal control bus cbcr y c clock and timing d a 73 72 71 75 27 38 25 26 34 33 32 36 54, 57, 60, 64, 74 53, 75 61 55 54 51 48 45 50 47 44 52, 56 41, 64 65 66 6, 14, 20, 29, 31, 39, 67, 69, 74 5, 13, 19, 28, 30, 37, 68, 70, 76 7 to 12, 35, 40 58, 60 y cbcr 15 to 18, 21 to 24 mp7 to mp0 reset sda scl sa rtci cdir rcv1 rcv2 v dddo (5) xtalo xtali llc v dda1 to v dda5 v refh1 v refh2 cvbs (1) v ssa1 res res res res red (2) green (3) blue (4) cur1 cur2 v refl1 v refl2 ap 57, 59 res sp n.c. v ddd1 to v ddd9 v ssd1 to v ssd9 y saa7124 saa7125 fig.3 block diagram; qfp80. (1) alternatively y or cvbs. (2) alternatively chroma or cr. (3) alternatively cvbs or yin. (4) alternatively cvbs or cb. (5) v1 devices only.
1996 nov 07 7 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 pinning symbol type pin description plcc84 lqfp64 qfp80 reset i 1 57 73 reset input, active low. after reset is applied, all digital i/os are in input mode. the i 2 c-bus receiver waits for the start condition. n.c. - 2 -- not connected v ssd1 i 3 6 6 digital ground 1 sa i 4 59 75 the i 2 c-bus slave address select input pin. low: slave address = 88h, high = 8ch. v ddd1 i 5 5 5 digital supply voltage 1 tp1 o 6 61 77 test pin outputs. leave open for normal operation. tp2 o 7 62 78 tp3 o 8 63 79 tp4 o 9 64 80 tp5 o 10 1 1 tp6 o 11 2 2 tp7 o 12 3 3 tp8 o 13 4 4 v ddd2 i 14 7 13 digital supply voltage 2 v ssd2 i 15 8 14 digital ground 2 n.c. - 16 - 7 not connected n.c. - 17 - 8 n.c. - 18 - 9 n.c. - 19 - 10 n.c. - 20 - 11 n.c. - 21 - 12 v ddd3 i 22 13 19 digital supply voltage 3 n.c. - 23 -- not connected v ssd3 i 24 14 20 digital ground 3 mp7 i 25 9 15 upper 4 bits of mpeg port. it is an input for ccir 656 style multiplexed cb, y, cr data. mp6 i 261016 mp5 i 27 11 17 mp4 i 281218 v ddd4 i 29 22 28 digital supply voltage 4 v ssd4 i 30 23 29 digital ground 4 mp3 i 311521 lower 4 bits of mpeg port. it is an input for ccir 656 style multiplexed cb, y, cr data. mp2 i 321622 mp1 i 331723 mp0 i 341824 rcv1 i/o 35 19 25 raster control 1 for video port. this pin receives/provides a vs/fs/fseq signal.
1996 nov 07 8 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 rcv2 i/o 36 20 26 raster control 2 for video port. this pin provides an hs pulse of programmable length or receives an hs pulse. rtci i 37 21 27 real time control input. if the llc clock is provided by an saa7111 or saa7151b, rtci should be connected to the rtco pin of the respective decoder to improve the signal quality. v ddd5 i 38 24 30 digital supply voltage 5 v ssd5 i 39 25 31 digital ground 5 n.c. - 40 - 35 not connected v ddd6 i 41 30 37 digital supply voltage 6 v ssd6 i 42 51 39 digital ground 6 n.c. - 43 - 40 not connected xtali i 44 26 32 crystal oscillator input (from crystal). if the oscillator is not used, this pin should be connected to ground. xtalo o 45 27 33 crystal oscillator output (to crystal). v dddo i 46 28 34 digital supply voltage for the internal oscillator; note 1 n.c. - 47 -- not connected llc i/o 48 29 36 line-locked clock. this is the 27 mhz master clock for the encoder. the i/o direction is set by the cdir pin. v ddd7 i 49 52 68 digital supply voltage 7 cdir i 50 31 38 clock direction. if cdir input is high, the circuit receives a clock signal, otherwise if cdir is low, llc is generated by the internal crystal oscillator. v ssd7 i 51 53 67 digital ground 7 v refl1 i 52 32 41 lower reference voltage 1 input for dacs; connect to analog ground. v refh1 i 53 33 42 upper reference voltage 1 input for dacs; connect via 100 nf capacitor to analog ground. v dda1 i 54 34 43 analog supply voltage 1 for dacs. blue o 55 35 44 analog output of the blue component. res i 56 - 45 reserved v dda2 i 57 36 46 analog supply voltage 2 for dacs. green o 58 37 47 analog output of green component. res i 59 - 48 reserved v dda3 i 60 38 49 analog supply voltage 3 for dacs. red o 61 39 50 analog output of red component. res i 62 - 51 reserved cur1 i 63 40 52 current input 1 for rgb ampli?ers; connect via 15 k w resistor to v dda . v dda4 i 64 41 53 analog supply voltage 4 for dacs. res i 65 - 54 reserved n.c. - 66 -- not connected symbol type pin description plcc84 lqfp64 qfp80
1996 nov 07 9 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 note 1. v1 devices only. v ssa1 i 67 42 55 analog ground 1 for the dacs. v ssa2 i - 43 - analog ground 2 for the dacs. cur2 i 68 44 56 current input 2 for rgb ampli?ers; connect via 15 k w resistor to v dda . res o 69 - 57 reserved n.c. - 70 - 58 not connected res o 71 - 59 reserved n.c. - 72 - 60 not connected cvbs o 73 45 61 analog output of the cvbs signal. v dda5 i 74 46 62 analog supply voltage 5 for dacs. v refh2 i 75 47 63 upper reference voltage 2 input for dacs; connect via 100 nf capacitor to analog ground. v refl2 i 76 48 64 lower reference voltage 2 input for dacs; connect to analog ground. ap i 77 49 65 test pin. connected to digital ground for normal operation. sp i 78 50 66 test pin. connected to digital ground for normal operation. v ssd8 i 79 58 69 digital ground 8 v ddd8 i 80 54 70 digital supply voltage 8 v ssd9 i81 - 74 digital ground 9 v ddd9 i 82 60 76 digital supply voltage 9 scl i 835571i 2 c-bus serial clock input. sda i/o 84 56 72 i 2 c-bus serial data input/output. symbol type pin description plcc84 lqfp64 qfp80
1996 nov 07 10 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.4 pin configuration; plcc84. (1) v1 devices only. handbook, full pagewidth saa7124 saa7125 mgg548 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 tp6 tp5 tp4 tp3 tp2 tp1 v ddd1 sa v ssd1 n.c. reset sda scl v ddd9 v ssd9 v ddd8 v ssd8 sp ap v refl2 v refh2 mp1 mp0 rcv1 rcv2 rtci v ddd5 v ssd5 n.c. v ddd6 v ssd6 n.c. xtali xtalo v dddo (1) n.c. llc v ddd7 cdir v ssd7 v refl1 v ref h1 v dda5 cvbs n.c. res n.c. res cur2 v ssa1 n.c. res v dda4 cur1 res red v dda3 res green v dda2 res blue v dda1 tp7 tp8 v ddd2 v ssd2 n.c. n.c. n.c. n.c. n.c. n.c. v ddd3 n.c. v ssd3 mp7 mp6 mp5 mp4 v ddd4 v ssd4 mp3 mp2
1996 nov 07 11 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.5 pin configuration; lqfp64 (v1 devices only). handbook, full pagewidth saa7124 saa7125 mgg547 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v refl2 v refh2 v dda5 cvbs cur2 v ssa2 v ssa1 v dda4 cur1 red v dda3 green v dda2 blue v dda1 v refh1 tp5 tp6 tp7 tp8 v ddd1 v ssd1 v ddd2 v ssd2 mp7 mp6 mp5 mp4 v ddd3 v ssd3 mp3 mp2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 tp4 tp3 tp2 tp1 v ddd9 sa v ssd8 reset sda scl v ddd8 v ssd7 v ddd7 v ssd6 sp ap mp1 mp0 rcv1 rcv2 rtci v ddd4 v ssd4 v ddd5 v ssd5 xtali xtalo v dddo llc v ddd6 cdir v refl1
1996 nov 07 12 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.6 pin configuration; qfp80. (1) v1 devices only. handbook, full pagewidth saa7124 saa7125 mgg549 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 n.c. res n.c. res cur2 v refl2 v refh2 v dda5 cvbs v ssa1 res v dda4 cur1 res red v dda3 res green v dda2 res blue v dda1 v refh1 v refl1 v ddd1 v ssd1 n.c. n.c. n.c. tp5 tp6 tp7 tp8 n.c. n.c. n.c. v ddd2 v ssd2 mp7 mp6 mp5 mp4 v ddd3 v ssd3 mp3 mp2 mp1 mp0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 rcv1 rcv2 rtci v ddd4 v ssd4 v ddd5 v ssd5 xtali xtalo v dddo (1) n.c. llc v ddd6 cdir v ssd6 n.c. tp4 tp3 tp2 tp1 v ddd9 sa v ssd9 reset sda scl v ddd8 v ssd8 v ddd7 v ssd7 sp ap 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1996 nov 07 13 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 functional description the digital video encoder (eco-denc) encodes digital luminance and colour difference signals into analog cvbs and simultaneously rgb signals. ntsc-m, pal b/g standards and sub-standards are supported. both interlaced and non-interlaced operation is possible for all standards. optionally, the input y, cb and cr data, digital-to-analog converted, is available at the analog rgb outputs. for applications that do not require rgb output, the device can be configured in such a way that s-video and twice cvbs is available (y at cvbs-dac, c at r-dac, and cvbs at g-dac and b-dac). the basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. luminance and chrominance signals are filtered in accordance with the standard requirements of rs-170-a and ccir 624 . for ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. for total filter transfer characteristics see figs 7, 8, 9, 10, 11 and 12. the dacs for y, c, and cvbs are realized with full 10-bit resolution, dacs for rgb with 9-bit resolution. the mpeg port (mp) accepts 8 line multiplexed cb, y, cr data. the 8-bit multiplexed cb-y-cr formats are ccir 656 (d1 format) compatible, but auxiliary codes such as sav and eav are decoded optionally for trigger purposes. a crystal-stable master clock (llc) of 27 mhz, which is twice the ccir line-locked pixel clock of 13.5 mhz, needs to be supplied externally. optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. it is also possible to connect a philips digital video decoder (saa7111 or saa7151b) in conjunction with a cref clock qualifier to eco-denc. via the rtci pin, connected to rtco of a decoder, information concerning actual subcarrier, pal-id, and if connected to saa7111, definite subcarrier phase can be inserted. the eco-denc synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. the encoder can be configured as slave with respect to rcv trigger inputs or auxiliary ccir 656 codes, or can be master to output horizontal and vertical trigger pulses. the ic also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with macrovision. a number of possibilities are provided for setting different video parameters such as: black and blanking level control colour subcarrier frequency variable burst amplitude etc. during reset ( reset = low) and after reset is released, all digital i/o stages are set to input mode. a reset forces the i 2 c-bus interface to abort any running bus transfer and sets register 3a to 03h, register 61 to 06h and registers 6bh and 6eh to 00h. all other control registers are not influenced by a reset. data manager in the data manager, real time arbitration on the data stream to be encoded is performed. optionally, the device can operate as a 100/75 colour bar test pattern generator without need for an external data source. encoder v ideo path the encoder generates out of y, u and v baseband signals luminance and colour subcarrier output signals, suitable for use as cvbs or separate y and c signals. luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). after having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with macrovision anti-taping, additional insertion of agc super-white pulses, programmable in height, is supported. in order to enable easy analog post filtering, luminance is interpolated from 13.5 mhz data rate to 27 mhz data rate, providing luminance in 10-bit resolution. this filter is also used to define smoothed transients for synchronization pulses and blanking period. for transfer characteristic of the luminance interpolation filter see figs 9 and 10.
1996 nov 07 14 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 chrominance is modified in gain (programmable separately for u and v), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 mhz data rate to 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for y and c output. for transfer characteristics of the chrominance interpolation filter see figs 7 and 8. the amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. the numeric ratio between y and c outputs is in accordance with set standards. c losed caption encoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number where data is to be encoded in, can be modified in a certain range. data clock frequency is in accordance with definition for ntsc-m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times horizontal line frequency. a nti - taping (saa7124 only ) for more information contact your nearest philips semiconductors sales office. rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, cb and cr signals are de-matrixed, 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. for transfer curves of luminance and colour difference components of rgb see figs 11 and 12. output interface/dacs in the output interface encoded both y and c signals are converted from digital-to-analog in 10-bit resolution. y and c signals are also combined to a 10-bit cvbs signal. red, green and blue signals (optionally cr, y, cb) are also converted from digital-to-analog, each providing a 9-bit resolution. all output occurs with the same processing delay. absolute amplitudes at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of conversion ranges. depending on control bits yc_en and demoff, different signal combinations are available at dacs #1 to #4. yc_en = demoff = low is the default configuration after reset. table 1 control of dac signals outputs of the dacs can be set together in two groups (#1 and #2 by downb, #3 and #4 by downa) via software control to minimum output voltage for either purpose. synchronization synchronization of the eco-denc is able to operate in two modes; slave mode and master mode. in the slave mode, the circuit accepts synchronization pulses at the bidirectional rcv1 port (or equivalently as frame synchronization from ccir 656 data stream). the timing and trigger behaviour related to rcv1 can be influenced by programming the polarity and on-chip delay of rcv1. active slope of rcv1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. if the horizontal phase is not to be influenced by rcv1, a horizontal pulse needs to be supplied at the rcv2 pin (or a horizontal synchronization from ccir 656 data stream). timing and trigger behaviour can also be influenced for rcv2. yc_en demoff dac1 dac2 dac3 dac4 0 0 cvbs r g b 0 1 cvbs cr y cb 1 0 vbs c cvbs cvbs 1 1 vbs c cvbs cvbs
1996 nov 07 15 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 if there are missing pulses at rcv1 and/or rcv2, the time base of eco-denc runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (with the incorrect phase) must occur. if the vertical and horizontal phase is derived from rcv1, rcv2 can be used for horizontal or composite blanking input or output. alternatively, the device can be triggered by auxiliary codes in a ccir 656 data stream at the mp port. in the master mode, the time base of the circuit continuously runs free. on the rcv1 port, the ic can output: a vertical sync signal (vs) with 3 or 2.5 lines duration, or; an odd/even signal which is low in odd fields, or; a field sequence signal (fseq) which is high in the first of 4, 8 fields respectively. on the rcv2 port, the ic can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. the polarity of both rcv1 and rcv2 is selectable by software control. field length is in accordance with to 50 hz or 60 hz standards, including non-interlaced options; start and end of its active part can be programmed. the active part of a field always starts at the beginning of a line, if the standard blanking option sblbn is not set. i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write only, except one readable status byte. two i 2 c-bus slave addresses are selected: 88h: low at pin sa 8ch: high at pin sa. input levels and formats eco-denc expects digital y, cb, cr data with levels (digital codes) in accordance with ccir 601 . for c and cvbs outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. for rgb (or y, cb and cr) outputs fixed amplification in accordance with ccir 601 is provided. reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. t ransformation r = y + 1.3707 (cr - 128) g=y - 0.3365 (cb - 128) - 0.6982 (cr - 128) b = y + 1.7324 (cb - 128). representation of r, g and b at the output is 9 bits at 27 mhz. table 2 8-bit multiplexed format (similar to ccir 656 ) time bits 01224567 sample cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 y 3 luminance pixel number 0123 colour pixel number 0 2
1996 nov 07 16 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 bit allocation map table 3 slave receiver (slave address 88h or 8ch) register function sub address data byte (1) d7 d6 d5 d4 d3 d2 d1 d0 null 00 00000000 null 39 00000000 i/o port control 3a cbenb 0 yc_en symp demoff 0 y2c uv2c null 42 00000000 null 59 00000000 chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, black level 5d gainu8 0 blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, blanking level, decoder type 5e gainv8 dectyp blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 blanking level vbi 5f 0 0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60 00000000 standard control 61 downb downa inpi ygs 0 scbw pal fise rtc enable burst amplitude 62 rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 rcv port control 6b srcv11 srcv10 trcv2 orcv1 prcv1 cblf orcv2 prcv2 trigger control 6c htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6d htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6e sblbn 0 phres1 phres0 0 0 flc1 flco
1996 nov 07 17 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 note 1. all bits marked 0 must be programmed to zero. closed caption 6f ccen1 ccen0 0 sccln4 sccln3 sccln2 sccln1 sccln0 rcv2 output start 70 rcv2s7 rcv2s6 rcv2s5 rcv2s4 rcv2s3 rcv2s2 rcv2s1 rcv2s0 rcv2 output end 71 rcv2e7 rcv2e6 rcv2e5 rcv2e4 rcv2e3 rcv2e2 rcv2e1 rcv2e0 msbs rcv2 output 72 0 rcv2e10 rcv2e9 rcv2e8 0 rcv2s10 rcv2s9 rcv2s8 null 73 00000000 null 74 00000000 null 75 00000000 null 76 00000000 null 77 00000000 null 78 00000000 null 79 00000000 first active line 7a fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7b lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 msbs vertical 7c 0 lal8 0 fal8 0000 null 7d 00000000 null 7e 00000000 null 7f 00000000 register function sub address data byte (1) d7 d6 d5 d4 d3 d2 d1 d0
1996 nov 07 18 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 i 2 c-bus format table 4 i 2 c-bus address; see table 5 table 5 explanation of table 4 notes 1. x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read, no subaddressing with read. 2. if more than 1 byte data is transmitted, then auto-increment of the subaddress is performed. slave receiver table 6 subaddress 3a s slave address ack subaddress ack data 0 ack -------- data n ack p part description s start condition slave address 1000100x or 1000110x (note 1) ack acknowledge, generated by the slave subaddress (note 2) subaddress byte data data byte -------- continued data bytes and acks p stop condition data byte logic level description uv2c 0 cb, cr data are twos complement. 1 cb, cr data are straight binary. default after reset. y2c 0 y data is twos complement. 1 y data is straight binary. default after reset. demoff 0 y, cb and cr for rgb dematrix is active. default after reset. 1 y, cb and cr for rgb dematrix is bypassed. symp 0 horizontal and vertical trigger is taken from rcv2 and rcv1 respectively. default after reset. 1 horizontal and vertical trigger is decoded out of ccir 656 compatible data at mp port. yc_en 0 output of cvbs and rgb signals. default after reset. 1 output of y, c, and cvbs, cvbs signals. cbenb 0 data from input ports is encoded. default after reset. 1 colour bar with ?xed colours is encoded. the luts are read in upward order from index 0 to index 7.
1996 nov 07 19 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 7 subaddress 5a table 8 subaddress 5b and 5d notes 1. gainu = - 2.17 nominal to +2.16 nominal. 2. gainu = - 2.05 nominal to +2.04 nominal. table 9 subaddress 5c and 5e notes 1. gainv = - 1.55 nominal to +1.55 nominal. 2. gainv = - 1.46 nominal to +1.46 nominal. data byte description value result chps phase of encoded colour subcarrier (including burst) relative to horizontal sync. can be adjusted in steps of 360/256 degrees tbf pal-b/g and data from input ports tbf pal-b/g and data from look-up table tbf ntsc-m and data from input ports tbf ntsc-m and data from look-up table data byte description conditions remarks gainu variable gain for cb signal; input representation accordance with ccir 601 white-to-black = 92.5 ire (1) gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire (2) gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal data byte description conditions remarks gainv variable gain for cr signal; input representation accordance with ccir 601 white-to-black = 92.5 ire (1) gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire (2) gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal
1996 nov 07 20 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 10 subaddress 5d notes 1. output black level/ire = blckl 25/63 + 24; recommended value: blckl = 60 (3ch) normal. 2. output black level/ire = blckl 26/63 + 24; recommended value: blckl = 45 (2dh) normal. table 11 subaddress 5e notes 1. output black level/ire = blnnl 25/63 + 17; recommended value: blnnl = 58 (3ah) normal. 2. output black level/ire = blnnl 26/63 + 17; recommended value: blnnl = 63 (3fh) normal. table 12 subaddress 5f data byte description conditions remarks blckl variable black level; input representation accordance with ccir 601 white-to-sync = 140 ire (1) blckl = 0 output black level = 24 ire blckl = 63 (3fh) output black level = 49 ire white-to-sync = 143 ire (2) blckl = 0 output black level = 24 ire blckl = 63 (3fh) output black level = 50 ire data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire (1) blnnl = 0 output blanking level = 17 ire blnnl = 63 (3fh) output blanking level = 42 ire white-to-sync = 143 ire (2) blnnl = 0 output blanking level = 17 ire blnnl = 63 (3fh) output blanking level = 43 ire dectyp rtci logic 0 real time control input from saa7151b logic 1 real time control input from saa7111 data byte description blnvb variable blanking level during vertical blanking interval is typically identical to value of blnnl
1996 nov 07 21 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 13 subaddress 61 table 14 subaddress 62a table 15 subaddress 62b data byte logic level description fise 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line pal 0 ntsc encoding (non-alternating v component) 1 pal encoding (alternating v component); default after reset scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 7 and 8) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 7 and 8); default after reset ygs 0 luminance gain for white - black 100 ire; default after reset 1 luminance gain for white - black 92.5 ire including 7.5 ire set-up of black inpi 0 pal switch phase is nominal; default after reset 1 pal switch phase is inverted compared to nominal downa 0 dacs for g and b (y and cb or cvbs and cvbs) in normal operational mode; default after reset 1 dacs for g and b (y and cb or cvbs and cvbs) forced to lowest output voltage downb 0 dacs for cvbs and r (cvbs and cr or vbs and c) in normal operational mode; default after reset 1 dacs for cvbs and r (cvbs and cr or vbs and c) forced to lowest output voltage data byte description conditions remarks bsta amplitude of colour burst; input representation in accordance with ccir 601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 102 (66h bsta = 0 to 1.25 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 72 (48h) bsta = 0 to 1.76 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 106 (6ah) bsta = 0 to 1.20 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 75 (4bh) bsta = 0 to 1.67 nominal data byte logic level description rtce 0 no real time control of generated subcarrier frequency 1 real time control of generated subcarrier frequency through saa7151b or saa7111 (timing see fig.15)
1996 nov 07 22 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 16 subaddress 63 to 66 (four bytes to program subcarrier frequency) note 1. examples: a) ntsc-m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal-b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). table 17 subaddress 67 to 6a data byte description conditions remarks fsc0 to fsc3 f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) see note 1 fsc3 = most signi?cant byte fsc0 = least signi?cant byte data byte description remark l21o0 ?rst byte of captioning data, odd ?eld lsb of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format l21o1 second byte of captioning data, odd ?eld l21e0 ?rst byte of extended data, even ?eld l21e1 second byte of extended data, even ?eld fsc round f fsc f llc ------- - 2 32 ? ? ?? =
1996 nov 07 23 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 18 subaddress 6b table 19 logic levels and function of srcv1 data byte logic level description prcv2 0 polarity of rcv2 as output is active high, rising edge is taken when input, respectively; default after reset 1 polarity of rcv2 as output is active low, falling edge is taken when input, respectively orcv2 0 pin rcv2 is switched to input; default after reset 1 pin rcv2 is switched to output cblf 0 if orcv2 = high, pin rcv2 provides an href signal (horizontal reference pulse that is de?ned by rcv2s and rcv2e, also during vertical blanking interval); default after reset if orcv2 = low and bit symp = low, signal input to rcv2 is used for horizontal synchronization only (if trcv2 = high); default after reset 1 if orcv2 = high, pin rcv2 provides a composite-blanking-not signal, this is a reference pulse that is de?ned by rcv2s and rcv2e, excluding vertical blanking interval, which is de?ned by fal and lal if orcv2 = low and bit symp = low, signal input to rcv2 is used for horizontal synchronization (if trcv2 = high) and as an internal blanking signal prcv1 0 polarity of rcv1 as output is active high, rising edge is taken when input; default after reset 1 polarity of rcv1 as output is active low, falling edge is taken when input orcv1 0 pin rcv1 is switched to input; default after reset 1 pin rcv1 is switched to output trcv2 0 horizontal synchronization is taken from rcv1 port (at bit symp = low) or from decoded frame sync of ccir 656 input (at bit symp = high); default after reset 1 horizontal synchronization is taken from rcv2 port (at bit symp = low) srcv1 - de?nes signal type on pin rcv1; see table 19 data byte as output as input function srcv11 srcv10 0 0 vs vs vertical sync each ?eld; default after reset 0 1 fs fs frame sync (odd/even) 1 0 fseq fseq ?eld sequence, vertical sync every fourth ?eld (pal = 0) or eighth ?eld (pal = 1) 1 1 not applicable not applicable -
1996 nov 07 24 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 20 subaddress 6c and 6d table 21 subaddress 6d table 22 subaddress 6e table 23 logic levels and function of phres table 24 logic levels and function of flc data byte description htrig sets the horizontal trigger phase related to signal on rcv1 or rcv2 input (or to decoded ccir 656 data) values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed increasing htrig decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig = tbfh (tbfh) data byte description vtrig sets the vertical trigger phase related to signal on rcv1 input (or to decoded ccir 656 data) increasing vtrig decreases delays of all internally generated timing signals, measured in half lines variation range of vtrig = 0 to 31 (1fh) data byte logic level description sblbn 0 vertical blanking is de?ned by programming of fal and lal; default after reset 1 vertical blanking is forced in accordance with ccir 624 (50 hz) or rs170a (60 hz) phres - selects the phase reset mode of the colour subcarrier generator; see table 23 flc - ?eld length control; see table 24 data byte function phres1 phres0 0 0 no reset or reset via rtci from saa7111 if bit rtce = 1; default after reset 0 1 reset every two lines 1 0 reset every eight ?elds 1 1 reset every four ?elds data byte function flc1 flc0 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 1 1 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz
1996 nov 07 25 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 table 25 subaddress 6f table 26 logic levels and function of ccen table 27 subaddress 70 to 72 table 28 subaddress 7a to 7c s ubaddresses in subaddresses 5b, 5c, 5d, 5e and 62 all ire values are rounded up. data byte description ccen enables individual line 21 encoding; see table 26 sccln selects the actual line, where closed caption or extended data are encoded line = (sccln + 4) for m-systems line = (sccln + 1) for other systems data byte function ccen1 ccen0 0 0 line 21 encoding off 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds data byte description rcv2s start of output signal on rcv2 pin values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed ?rst active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2s = tbfh (tbfh) rcv2e end of output signal on rcv2 pin values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2e = tbfh (tbfh) data byte description fal ?rst active line = fal + 4 for m-systems, = fal + 1 for other systems, measured in lines fal = 0 coincides with the ?rst ?eld synchronization pulse lal last active line = lal + 3 for m-systems, = lal for other system, measured in lines lal = 0 coincides with the ?rst ?eld synchronization pulse
1996 nov 07 26 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 slave transmitter table 29 slave transmitter (slave address 89h or 8dh) table 30 no subaddress register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte - ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e data byte logic level description ver - version identi?cation of the device. it will be changed with all versions of the ic that have different programming models. current version is 100 binary. ccrdo 1 closed caption bytes of the odd ?eld have been encoded. 0 the bit is reset after information has been written to the subaddresses 67 and 68. it is set immediately after the data has been encoded. ccrde 1 closed caption bytes of the even ?eld have been encoded. 0 the bit is reset after information has been written to the subaddresses 69 and 6a. it is set immediately after the data has been encoded. fseq 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pa l = 8 ?elds. 0 not ?rst ?eld of a sequence. o_e 1 during even ?eld. 0 during odd ?eld.
1996 nov 07 27 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.7 chrominance transfer characteristic 1. handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) (1) scbw = 1. (2) scbw = 0. fig.8 chrominance transfer characteristic 2. (1) scbw = 1. (2) scbw = 0. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2)
1996 nov 07 28 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.9 luminance transfer characteristic 1. (1) total luminance of y and cvbs. handbook, full pagewidth 6 8 10 12 14 6 0 024 mgg556 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) fig.10 luminance transfer characteristic 2. handbook, halfpage 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) (1) detailed luminance of y and cvbs.
1996 nov 07 29 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.11 luminance transfer characteristic in rgb. handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb708 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.12 colour difference transfer characteristic in rgb. handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb706 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db)
1996 nov 07 30 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 characteristics v ddd = 4.75 to 5.25 v; t amb = 0 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit supplies v dda analog supply voltage 4.75 5.25 v v ddd digital supply voltage 4.75 5.25 v i dda analog supply current note 1 - 60 ma i ddd digital supply current note 1 - 100 ma inputs v il low level input voltage (except sda, scl, ap, sp and xtali) - 0.5 +0.8 v v ih high level input voltage (except llc, sda, scl, ap, sp and xtali) 2.0 v ddd + 0.5 v high level input voltage (llc) 2.4 v ddd + 0.5 v i li input leakage current - 1 m a c i input capacitance clocks - 10 pf data - 8pf i/os at high impedance - 8pf outputs v ol low level output voltage (except sda and xtalo) note 2 0 0.6 v v oh high level output voltage (except llc, sda, and xtalo) note 2 2.4 v ddd + 0.5 v high level output voltage (llc) note 2 2.6 v ddd + 0.5 v i 2 c-bus; sda and scl v il low level input voltage - 0.5 +1.5 v v ih high level input voltage 3.0 v ddd + 0.5 v i i input current v i = low or high - 10 +10 m a v ol low level output voltage (sda) i ol =3ma - 0.4 v i o output current during acknowledge 3 - ma clock timing (llc) t llc cycle time note 3 34 41 ns d duty factor t high /t llc note 4 40 60 % t r rise time note 3 - 5ns t f fall time note 3 - 6ns input timing t su;dat input data set-up time (any other except cdir, scl, sda, reset, ap and sp) 6 - ns t hd;dat input data hold time (any other except cdir, scl, sda, reset, ap and sp) 3 - ns
1996 nov 07 31 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 notes 1. at maximum supply voltage with highly active input signals. 2. the levels have to be measured with load circuits of 1.2 k w to 3.0 v (standard ttl load) and c l = 25 pf. 3. the data is for both input and output direction. 4. with llc in input mode. in output mode, with a crystal connected to xtalo/xtali duty factor is typically 50%. 5. if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. for full digital range, without load, v dda = 5.0 v. the typical voltage swing is 2.0 v, the typical minimum output voltage (digital zero at dac) is 0.2 v. crystal oscillator f n nominal frequency (usually 27 mhz) 3rd harmonic - 30 mhz d f/f n permissible deviation of nominal frequency note 5 - 50 +50 10 - 6 c rystal specification t amb operating ambient temperature 0 70 c c l load capacitance 8 - pf r s series resistance - 80 w c 1 motional capacitance (typical) 1.5 - 20% 1.5 + 20% ff c 0 parallel capacitance (typical) 3.5 - 20% 3.5 + 20% pf data and reference signal output timing c l output load capacitance 7.5 40 pf t h output hold time 4 - ns t d output delay time - 25 ns chroma, y, cvbs and rgb outputs v o(p-p) output signal voltage (peak-to-peak value) note 6 1.9 2.1 v r int internal serial resistance 18 35 w r l output load resistance 80 -w b output signal bandwidth of dacs - 3db 10 - mhz ile lf integral linearity error of dacs - 4 lsb dle lf differential linearity error of dacs - 1 lsb symbol parameter conditions min. max. unit
1996 nov 07 32 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.13 clock data timing. handbook, full pagewidth mbe742 llc clock output 0.6 v 1.5 v 2.6 v 2.0 v 0.8 v 2.4 v 0.6 v input data output data not valid valid valid not valid valid valid llc clock input 0.8 v 1.5 v 2.4 v t high t hd; dat t llc t high t llc t d t hd; dat t hd; dat t su; dat t f t f t r t r fig.14 functional timing. the data demultiplexing phase is coupled to the internal horizontal phase. the phase of the rcv2 signal is programmed to 0f2h (110h for 50 hz) in this example in output mode (rcv2s). handbook, full pagewidth mp(n) llc cb(0) y(0) cr(0) y(1) cb(2) rcv2 mgb699
1996 nov 07 33 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 fig.15 rtci timing. (1) sequence bit: pal = logic 0 then (r - y) line normal; pal = logic 1 then (r - y) line inverted. ntsc = logic 0 then no change. (2) reserved bits: 235 with 50 hz systems; 232 with 60 hz systems. (3) only from saa7111 decoder. (4) saaa7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit. handbook, full pagewidth 128 13 14 19 67 68 01 0 0 21 rtci hpll increment fscpll increment (4) h/l transition count start 4 bits reserved valid sample invalid sample not used in saa7124/25 sequence bit (1) reset bit (3) 5 bits reserved 8/llc reserved (2) mgg557 low time slot:
1996 nov 07 34 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 application information a ndbook, full pagewidth mgg553 15 k w 0.1 m f 0.1 m f 0.1 m f 10 pf 10 pf 10 m h 1 nf x1 27.0 mhz 3rd harmonic 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd + 5 v digital + 5 v digital v ddd1 v ddd2 v ddd3 v ddd4 v ddd5 v ddd6 v ddd7 v ddd8 v ddd9 5 14 22 29 38 41 49 80 82 12 w 75 w 73 35 w (1) 74 w 75 w 61 35 w (1) 74 w 75 w 58 35 w (1) 74 w 75 w 55 35 w (1) v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa + 5 v analog dac1 dac2 dac3 dac4 digital inputs and outputs xtali xtalo 44 45 cvbs 1.23 v (p-p) (2) red 0.7 v (p-p) (2) green 0.7 v (p-p) (2) blue 0.7 v (p-p) (2) 0.1 m f v ssd v ssa v dddo (4) v dda4 v refh cur v dda1 v dda2 v dda3 v dda5 46 64 53, 75 63, 68 54 57 60 74 v refl 52, 76 v ssd1 to v ssd9 v ssa 3, 15, 24, 30, 39, 42, 51, 79, 81 saa7124 saa7125 67 v ssa1 v ssa v ssa v ssa v ssa (3) fig.16 application environment of the eco-denc; plcc84. (1) typical value. (2) for 100 100 colour bar. (3) philips 12nc ordering code: 9922 520 30003. (4) v1 devices only.
1996 nov 07 35 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 db ook, full pagewidth mgg554 15 k w 0.1 m f 0.1 m f 0.1 m f 10 pf 10 pf 10 m h 1 nf x1 27.0 mhz 3rd harmonic 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd + 5 v digital + 5 v digital v ddd1 v ddd2 v ddd3 v ddd4 v ddd5 v ddd6 v ddd7 v ddd8 v ddd9 5 7 13 22 24 30 52 54 60 12 w 75 w 45 35 w (1) 74 w 75 w 39 35 w (1) 74 w 75 w 37 35 w (1) 74 w 75 w 35 35 w (1) v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa + 5 v analog dac1 dac2 dac3 dac4 digital inputs and outputs xtali xtalo 20 27 cvbs 1.23 v (p-p) (2) red 0.7 v (p-p) (2) green 0.7 v (p-p) (2) blue 0.7 v (p-p) (2) 0.1 m f v ssd v ssa v dddo v dda4 v refh cur v dda1 v dda2 v dda3 v dda5 28 41 33, 47 40, 44 34 36 38 46 v refl 32, 48 v ssd1 to v ssd8 v ssa 6, 8, 14, 23, 25, 51, 53, 58 saa7124 saa7125 42, 43 v ssa1 v ssa v ssa v ssa v ssa (3) fig.17 application environment of the eco-denc; lqfp64 (v1 devices only). (1) typical value. (2) for 100 100 colour bar. (3) philips 12nc ordering code: 9922 520 30003.
1996 nov 07 36 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 d book, full pagewidth mgg555 15 k w 0.1 m f 0.1 m f 0.1 m f 10 pf 10 pf 10 m h 1 nf x1 27.0 mhz 3rd harmonic 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd + 5 v digital + 5 v digital v ddd1 v ddd2 v ddd3 v ddd4 v ddd5 v ddd6 v ddd7 v ddd8 v ddd9 5 13 19 28 30 37 68 70 76 12 w 75 w 61 35 w (1) 74 w 75 w 50 35 w (1) 74 w 75 w 47 35 w (1) 74 w 75 w 44 35 w (1) v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa + 5 v analog dac1 dac2 dac3 dac4 digital inputs and outputs xtali xtalo 32 33 cvbs 1.23 v (p-p) (2) red 0.7 v (p-p) (2) green 0.7 v (p-p) (2) blue 0.7 v (p-p) (2) 0.1 m f v ssd v ssa v dddo (4) v dda4 v refh cur v dda1 v dda2 v dda3 v dda5 34 53 42, 63 52, 56 43 46 49 62 v refl 41, 64 v ssd1 to v ssd8 v ssa 6, 14, 20, 29, 31 39, 67, 69, 74 saa7124 saa7125 55 v ssa1 v ssa v ssa v ssa v ssa (3) fig.18 application environment of the eco-denc; qfp80. (1) typical value. (2) for 100 100 colour bar. (3) philips 12nc ordering code: 9922 520 30003. (4) v1 devices only.
1996 nov 07 37 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 package outlines references outline version european projection issue date iec jedec eiaj note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot189-2 54 74 84 1 11 12 32 53 33 75 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e h v m b d z d a z e e v m a pin 1 index 0 5 10 mm scale 92-11-17 95-03-11 plcc84: plastic leaded chip carrier; 84 leads sot189-2 unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b mm 4.57 4.19 0.51 3.30 0.53 0.33 0.021 0.013 1.27 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) d (1) 29.41 29.21 h d 30.35 30.10 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.13 a 3 0.25 0.01 0.05 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 1.158 1.150 29.41 29.21 1.158 1.150 1.195 1.185 30.35 30.10 1.195 1.185 e e e d 28.70 27.69 1.130 1.090 28.70 27.69 1.130 1.090 0.085 0.032 0.026 0.048 0.042 e e inches d e
1996 nov 07 38 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 0.69 0.59 1.45 1.05 7 0 o o 0.12 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 94-01-07 95-12-19 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p q detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
1996 nov 07 39 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.30 0.10 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 0.2 19.0 18.4 1.4 1.2 1.2 0.8 7 0 o o 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.4 1.0 sot318-3 95-02-04 95-04-25 d (1) (1) (1) 20.1 19.9 h d 25.0 24.4 e z 1.0 0.6 d b p e q e a 1 a l p q detail x l (a ) 3 b 24 y c d h b p e h a 2 v m b d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index 2.35 x w m w m 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 2.35 mm); body 14 x 20 x 2.8 mm sot318-3 a max. 3.25
1996 nov 07 40 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all plcc and qfp packages. the choice of heating method may be influenced by larger plcc or qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering plcc wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). m ethod (plcc and qfp) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 nov 07 41 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 nov 07 42 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 notes
1996 nov 07 43 philips semiconductors preliminary speci?cation digital video encoder (eco-denc) saa7124; saa7125 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 657021/1200/01/pp44 date of release: 1996 nov 07 document order number: 9397 750 01467

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